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myson technology MTV212A32 (rev. 1.2) 8051 embedded monitor controller mask rom type this datasheet contains new product information. myson technology reserves the rights to modify the product specification without notice. no liability is assumed as a result of the use of this product. no rights under any patent accompany the sale of the product. revision 1.2 - 1 - 2000/07/04 features 8051 core, 12mhz operating frequency. 512-byte ram, 32k-byte program mask-rom. maximum 14 channels of 5v open-drain pwm dac. maximum 31 bi-directional i/o pins. sync processor for composite separation/insertion, h/v polarity/frequency check, polarity adjustment and programmable clamp pulse output. buil t-in self-test pattern generator with four free-running timings. built-in low power reset circuit. compliant with vesa ddc1/2b/2bi/2b+ standard. dual slave i ic addresses. single master iic interface for internal device communication. 3-channel 6-bit adc. watchdog timer with programmable interval. 40-pin dip, 42-pin sdip or 44-pin plcc package. general descriptions the MTV212A32 micro-controller is an 8051 cpu core embedded device specially tailored to monitor applications. it includes an 8051 cpu core, 512-byte sram, sync processor, 14 built-in pwm dacs, vesa ddc interface, 3-channel a/d converter and a 32k-byte internal program mask-rom. block diagram p1.0-7 p2.0-2 ,p2.4-7 p3.4-5 x1 p0.0-7 rd wr ale int1 x2 8051 core p3.0-2 rst p0.0-7 rd wr ale int1 xfr stout hblank vblank hsync vsync hclamp halfv halfh h/vsync control iscl isda hscl hsda ddc & iic interface adc ad0-2 14 channel pwm dac
myson technology MTV212A32 (rev. 1.2) revision 1.2 - 2 - 2000/07/04 device summary the MTV212A32 is one of the mtv212 family device. for other family devices information, please see the table below: part number usb rom ram package mtv212a16 no 16k 256 pdip40, sdip42, plcc44 mtv212a24 no 24k 512 pdip40, sdip42, plcc44 MTV212A32 no 32k 512 pdip40, sdip42, plcc44 MTV212A32u yes 32k 768 pdip40, sdip42, plcc44 mtv212a48u yes 48k 768 pdip40, sdip42, plcc44 mtv212a64u yes 64k 1024 pdip40, sdip42, plcc44 the usage of auxiliary ram (auxram) is limited for targeted mask rom, the allowable xbank (35h) bank selection is defined as the table below: part number ram xbnk2 xbnk1 xbnk0 mtv212a16 256 - - - mtv212a24 512 0 0 0 0 0 1 MTV212A32 512 0 0 0 0 0 1 MTV212A32u 768 0 0 0 0 0 1 0 1 0 0 1 1 mtv212a48u 768 0 0 0 0 0 1 0 1 0 0 1 1 mtv212a64u 1024 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1
myson technology MTV212A32 (rev. 1.2) revision 1.2 - 3 - 2000/07/04 pin connection MTV212A32 40 pin pdip da2/p5.2 40 1 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 da1/p5.1 da0/p5.0 rst vdd vss x2 x1 isda/p3.4/t0 iscl/p3.5/t1 stout/p4.2 p2.2/ad2 p1.0 p1.1 p3.2/int0 p1.2 p1.3 p1.4 p1.5 p1.6 hsync da3/p5.3 vsync da4/p5.4 da8/halfh da9/halfv da5/p5.5 hblank/p4.1 da7/hclamp da6/p5.6 vblank/p4.0 p2.7/da13 p2.5/da11 p2.4/da10 p2.6/da12 hscl/p3.0/rxd p2.0/ad0 p2.1/ad1 hsda/p3.1/txd p1.7 MTV212A32 42 pin sdip da2/p5.2 40 1 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 da1/p5.1 da0/p5.0 rst vdd vss x2 x1 isda/p3.4/t0 iscl/p3.5/t1 stout/p4.2 p2.2/ad2 p1.0 p1.1 p3.2/int0 p1.2 p1.3 nc nc nc hsync da3/p5.3 vsync da4/p5.4 da8/halfh da9/halfv da5/p5.5 hblank/p4.1 da7/hclamp da6/p5.6 vblank/p4.0 p1.6 p2.4/da10 p1.5 hscl/p3.0/rxd p2.0/ad0 p2.1/ad1 hsda/p3.1/txd p1.7 42 41 p2.5/da11 p2.6/da12 p1.4 MTV212A32 44 pin plcc 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 p1.6 24 p1.7 p2.1/ad1 p1.5 p2.0/ad0 hsda/p3.1/txd p1.1 p3.2/int0 p1.2 p1.3 p1.4 23 22 21 20 28 27 26 25 nc 6 5 4 3 2 1 44 43 42 41 40 nc nc da0/p5.0 da1/p5.1 da2/p5.2 vsync hsync da3/p5.3 da4/p5.4 da5/p5.5 19 18 rst vdd vss x2 x1 isda/p3.4/t0 iscl/p3.5/t1 stout/p4.2 p2.2/ad2 p1.0 nc p2.4/da10 hscl/p3.0/rxd p2.5/da11 p2.6/da12 da8/halfh da9/halfv hblank/p4.1 da7/hclamp da6/p5.6 vblank/p4.0 p2.7/da13
myson technology MTV212A32 (rev. 1.2) revision 1.2 - 4 - 2000/07/04 pin description name type # description da2/p5.2 i/o 1 pwm dac output (5v open drain) / general purpose i/o (5v open drain). da1/p5.1 i/o 2 pwm dac output (5v open drain) / general purpose i/o (5v open drain). da0/p5.0 i/o 3 pwm dac output (5v open drain) / general purpose i/o (5v open drain). rst i 4 active high reset. vdd - 5 positive power supply. vss - 6 ground. x2 o 7 oscillator output. x1 i 8 oscillator input. isda/p3.4/t0 i/o 9 master iic data (5v open drain) / general purpose i/o (8051 standard) / t0 (8051 standard). iscl/p3.5/t1 i/o 10 master iic clock (5v open drain) / general purpose i/o (8051 standard) / t1 (8051 standard). stout/p4.2 o 11 self-test video output (cmos) / general purpose output (cmos). p2.2/ad2 i/o 12 general purpose i/o (mask option as cmos output or 8051 standard) / adc input. p1.0 i/o 13 general purpose i/o (mask option as cmos output or 8051 standard). p1.1 i/o 14 general purpose i/o (mask option as cmos output or 8051 standard). p3.2/int0 i 15 general purpose input / int0. p1.2 i/o 16 general purpose i/o (mask option as cmos output or 8051 standard). p1.3 i/o 17 general purpose i/o (mask option as cmos output or 8051 standard). p1.4 i/o 18 general purpose i/o (mask option as cmos output or 8051 standard). p1.5 i/o 19 general purpose i/o (mask option as cmos output or 8051 standard). p1.6 i/o 20 general purpose i/o (mask option as cmos output or 8051 standard). p1.7 i/o 21 general purpose i/o (mask option as cmos output or 8051 standard). p2.1/ad1 i/o 22 general purpose i/o (mask option as cmos output or 8051 standard) / adc input. p2.0/ad0 i/o 23 general purpose i/o (mask option as cmos output or 8051 standard) / adc input. hsda/p3.1/txd i/o 24 slave iic data (5v open drain) / general purpose i/o (8051 standard) / txd (8051 standard). hscl/p3.0/rxd i/o 25 slave iic clock (5v open drain) / general purpose i/o (8051 standard) / rxd (8051 standard). p2.4/da10 i/o 26 general purpose i/o (mask option as cmos output or 8051 standard) / pwm dac output (cmos). p2.5/da11 i/o 27 general purpose i/o (mask option as cmos output or 8051 standard) / pwm dac output (cmos). p2.6/da12 i/o 28 general purpose i/o (mask option as cmos output or 8051 standard) / pwm dac output (cmos). p2.7/da13 i/o 29 general purpose i/o (mask option as cmos output or 8051 standard) / pwm dac output (cmos). da6/p5.6 i/o 30 pwm dac output (cmos) / general purpose i/o (mask option as cmos output or open drain i/o). da7/hclamp o 31 pwm dac output (cmos) / hsync clamp pulse output (cmos). vblank/p4.0 o 32 vertical blank (cmos) / general purpose output (cmos). hblank/p4.1 o 33 horizontal blank (cmos) / general purpose output (cmos). da9/halfv o 34 pwm dac output (5v open drain) / vsync half freq. output (5v open drain). da8/halfh o 35 pwm dac output (5v open drain) / hsync half freq. output (5v open drain). da5/p5.5 i/o 36 pwm dac output (cmos) / general purpose i/o (mask option as cmos output or open drain i/o). da4/p5.4 i/o 37 pwm dac output (cmos) / general purpose i/o (mask option as cmos output or open drain i/o). da3/p5.3 i/o 38 pwm dac output (cmos) / general purpose i/o (mask option as cmos output or open drain i/o). hsync i 39 horizontal sync or composite sync input. vsync i 40 vertical sync input.
myson technology MTV212A32 (rev. 1.2) revision 1.2 - 5 - 2000/07/04 pin configuration a ? cmos output pin ? means it can sink and drive at least 4ma current. it ? s not recommended to use such pin as input fuction. a ? 5v open drain pin ? means it can sink at least 4ma current but only drive 10~20ua to vdd. it can be used as input or output function and need an external pull up resistor. a ? 8051 standard pin ? is a pseudo open drain pin. it can sink at least 4ma current when output low level, and drive at least 4ma current for 160ns when output transit from low to high, then keep drive 100ua to maintain the pin at high level. it can be used as input or output function. it need an external pull up resistor when drive heavy load device. functional descriptions 1. 8051 cpu core MTV212A32 includes all 8051 functions with the following exceptions: 1.1 psen, ale, rd and wr pins are disabled. the external ram access is restricted to xfrs within the MTV212A32. 1.2 port0, port3.3, port3.6 and port3.7 are not general-purpose i/o ports. they are dedicated to monitor special application. 1.3 int1 input pin is not provided, it is connected to special interrupt sources. 1.4 port2 are shared with special fu n ction pins. in addition, there are 2 timers, 5 interrupt sources and serial interface compatible with the standard 8051. note: all registers listed in this document reside in external ram area (xfr). for internal ram memory map please refer to 8051 spec. 2. memory allocation 2.1 internal special function registers ( sfr) the sfr is a group of registers that are the same as standard 8051. 2.2 internal ram there are total 256 bytes internal ram in MTV212A32, same as standard 8052. 2.3 external special function registers (xfr) the xfr is a group of registers allocated in the 8051 external ram area 00h - 7fh. most of the registers are used for monitor control or pwm dac. program can initialize ri value and use "movx" instruction to access these registers. 2.4 auxiliary ram (auxram) there are total 256 bytes auxiliary ram allocated in the 8051 external ram area 80h - ffh. the auxram is divided into two banks, selected by xbank register. program can initialize ri value and use "movx" instruction to access the auxram.
myson technology MTV212A32 (rev. 1.2) revision 1.2 - 6 - 2000/07/04 3. chip configuration the chip configuration registers define the chip pins function, as well as the functional blocks' connection, configuration and frequency. reg name addr bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 padmod 30h (w) da13e da12e da11e da10e ad3e ad2e ad1e ad0e padmod 31h (w) p56e p55e p54e p53e p52e p51e p50e padmod 32h (w) hiice iiice hlfve hlfhe hclpe p42e p41e p40e option 33h (w) pwmf div253 fclke iicpass enscl msel miicf1 miicf0 option 34h (w) slvabs1 slvabs0 xbank 35h (r/w) xbnk2 xbnk1 xbnk0 padmod (w ) : pad mode control registers. (all are "0" in chip reset) da13e = 1 ? pin ? p2.7/da13 ? is da13. = 0 ? pin ? p2.7/da13 ? is p2.7. da12e = 1 ? pin ? p2.6/da12 ? is da12. = 0 ? pin ? p2.6/da12 ? is p2.6. da11e = 1 ? pin ? p2.5/da11 ? is da11. = 0 ? pin ? p2.5/da11 ? is p2.5. da10e = 1 ? pin ? p2.4/da10 ? is da10. = 0 ? pin ? p2.4/da10 ? is p2.4. ad3e = 1 ? no action = 0 ? no action ad2e = 1 ? pin ? p2.2/ad2 ? is ad2. = 0 ? pin ? p2.2/ad2 ? is p2.2. ad1e = 1 ? pin ? p2.1/ad1 ? is ad1. = 0 ? pin ? p2.1/ad1 ? is p2.1. ad0e = 1 ? pin ? p2.0/ad0 ? is ad0. = 0 ? pin ? p2.0/ad0 ? is p2.0. p56e = 1 ? pin ? da6/p5.6 ? is p5.6. = 0 ? pin ? da6/p5.6 ? is da6. p55e = 1 ? pin ? da5/p5.5 ? is p5.5. = 0 ? pin ? da5/p5.5 ? is da5. 00h 7fh 80h ffh auxram accessible by indirect external ram addressing (xbank=0)(using movx a ,@ ri instruction) xfr accessible by indirect external ram addressing (using movx a ,@ ri instruction auxram accessible by indirect external ram addressing (xbank=1)(using movx a ,@ ri instruction) 00h 7fh 80h ffh internal ram accessible by indirect addressing only (using mov a ,@ri instruction) internal ram accessible by direct and indirect addressing sfr accessible by direct addressing
myson technology MTV212A32 (rev. 1.2) revision 1.2 - 7 - 2000/07/04 p54e = 1 ? pin ? da4/p5.4 ? is p5.4. = 0 ? pin ? da4/p5.4 ? is da4. p53e = 1 ? pin ? da3/p5.3 ? is p5.3. = 0 ? pin ? da3/p5.3 ? is da3. p52e = 1 ? pin ? da2/p5.2 ? is p5.2. = 0 ? pin ? da2/p5.2 ? is da2. p51e = 1 ? pin ? da1/p5.1 ? is p5.1. = 0 ? pin ? da1/p5.1 ? is da1. p50e = 1 ? pin ? da0/p5.0 ? is p5.0. = 0 ? pin ? da0/p5.0 ? is da0. hiice = 1 ? pin ? hscl/p3.0/rxd ? is hscl ; pin ? hsda/p3.1/txd ? is hsda. = 0 ? pin ? hscl/p3.0/rxd ? is p3.0/rxd; pin ? hsda/p3.1/txd ? is p3.1/txd. iiice = 1 ? pin ? isda/p3.4/t0 ? is isda; pin ? iscl/p3.5/t1 ? is iscl. = 0 ? pin ? isda/p3.4/t0 ? is p3.4/t0; pin ? iscl/p3.5/t1 ? is p3.5/t1. hlfve = 1 ? pin ? da9/halfv ? is vsync half frequency output. = 0 ? pin ? da9/halfv ? is da9. hlfhe = 1 ? pin ? da8/halfh ? is hsync half frequency output. = 0 ? pin ? da8/halfh ? is da8. hclpe = 1 ? pin ? da7/hclamp ? is hsync clamp pulse output. = 0 ? pin ? da7/hclamp ? is da7. p42e = 1 ? pin ? stout/p4.2 ? is p4.2. = 0 ? pin ? stout/p4.2 ? is stout. p41e = 1 ? pin ? hblank/p4.1 ? is p4.1. = 0 ? pin ? hblank/p4.1 ? is hblank. p40e = 1 ? pin ? vblank/p4.0 ? is p4.0. = 0 ? pin ? vblank/p4.0 ? is vblank. option (w ) : chip option configuration (all are "0" in chip reset) . pwmf = 1 ? select 94khz pwm frequency. = 0 ? select 47khz pwm frequency. div253 = 1 ? pwm pulse width is 253 step resolution. = 0 ? pwm pulse width is 256 step resolution. fclke = 1 ? double cpu clock freq. iicpass = 1 ? hscl/hsda pin bypass to iscl/isda pin in ddc2 mode. = 0 ? separate master and slave iic block. enscl = 1 ? enable slave iic block to hold hscl pin low while MTV212A32 can't catch-up the external master's speed. msel = 1 ? master iic block connect to hscl/hsda pins. = 0 ? master iic block connect to iscl/isda pins. miicf1 ,miicf0 = 1,1 ? select 400khz master iic frequency. = 1,0 ? select 200khz master iic frequency. = 0,1 ? select 50khz master iic frequency. = 0,0 ? select 100khz master iic frequency. slvabs1 ,slvabs0 : slave iic block a's slave address length. = 1,0 ? 5-bits slave address. = 0,1 ? 6-bits slave address. = 0,0 ? 7-bits slave address. xbank (r/w ) : auxiliary ram bank switch. xbnk [2:0] = 0 ? select auxram bank 0. = 1 ? select auxram bank 1. = 2 ? select auxram bank 0. = 3 ? select auxram bank 1.
myson technology MTV212A32 (rev. 1.2) revision 1.2 - 8 - 2000/07/04 = 4 ? select auxram bank 0. = 5 ? select auxram bank 1. 4. extra i/o the extra i/o is a group of i/o pins located in xfr area. port4 is output mode only. port5 can be used as both output and input, because port5's pin is open drain type, user must write port5's corresponding bit to "1" in input mode. reg name addr bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 port4 38h (w) p42 p41 p40 port5 39h (r/w) p56 p55 p54 p53 p52 p51 p50 port4 (w ) : port 4 data output value. port5 (r/w ) : port 5 data input/output value. 5. pwm dac each pwm dac converter's output pulse width is controlled by an 8-bit register in xfr. the frequency of pwm clk is 47khz or 94khz, selected by pwmf. and the total duty cycle step of these dac outputs is 253 or 256, selected by div253. if div253=1, writing fdh/feh/ffh to dac register generates stable high output. if div253=0, the output will pulse low at least once even if the dac register's content is ffh. writing 00h to dac register generates stable low output. reg name addr bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 da0 20h (r/w) pulse width of pwm dac 0 da1 21h (r/w) pulse width of pwm dac 1 da2 22h (r/w) pulse width of pwm dac 2 da3 23h (r/w) pulse width of pwm dac 3 da4 24h (r/w) pulse width of pwm dac 4 da5 25h (r/w) pulse width of pwm dac 5 da6 26h (r/w) pulse width of pwm dac 6 da7 27h (r/w) pulse width of pwm dac 7 da8 28h (r/w) pulse width of pwm dac 8 da9 29h (r/w) pulse width of pwm dac 9 da10 2ah (r/w) pulse width of pwm dac 10 da11 2bh (r/w) pulse width of pwm dac 11 da12 2ch (r/w) pulse width of pwm dac 12 da13 2dh (r/w) pulse width of pwm dac 13 da0-13 (r/w ) : the output pulse width control for da0-13. * all of pwm dac converters are centered with value 80h after power on. 6. h/v sync processing the h/v sync processing block performs the functions of composite signal separation/insertion , sync inputs presence check, frequency counting, polarity detection and control, as well as the protection of vblank output while vsync speed up in high ddc communication clock rate. the present and frequency function block treat any pulse shorter than one osc period as noise.
myson technology MTV212A32 (rev. 1.2) revision 1.2 - 9 - 2000/07/04 h/v sync processor block diagram 6.1 composite sync separation/insertion the MTV212A32 continuously monitors the input hsync, if the vertical sync pulse can be extracted from the input, a cvpre flag is set and user can select the extracted "cvsync" for the source of polarity check, frequency count, and vblank output. the cvsync will have 8us delay compared to the original signal. the MTV212A32 can also insert pulse to hblank output during composite vsync ? s active time. the insert pulse ? s width is 1/8 hsync period and the insertion frequency can adapt to original hsync. 6.2 h/v frequency counter MTV212A32 can discriminate hsync/vsync frequency and saves the information in xfrs. the 14 bits hcounter counts the time of 64xhsync period, then load the result into the hcnth/hcntl latch. the output value will be [(128000000/h-freq) - 1], updated once per vsync/cvsync period when vsync/cvsync is present or continuously updated when vsync/cvsync is non-present. the 12 bits vcounter counts the time between two vsync pulses, then load the result into the vcnth/vcntl latch. the output value will be (62500/v-freq), updated every vsync/cvsync period. an extra overflow bit indicates the condition of h/v counter overflow. the vfchg/ hfchg interrupt is set when vcnt/hcnt value changes or overflow. table 4.2.1 and table 4.2.2 shows the hcnt/vcnt value under the operations of 12mhz. hself hpol cvpre vbpl vsync digital filter polarity check & sync seperator vpre present check vfreq vpol polarity check & freq. count xor vblank vself xor hsync digital filter cvsync present check hpre hfreq present check & freq. count hbpl xor hblank xor composite pulse insert
myson technology MTV212A32 (rev. 1.2) revision 1.2 - 10 - 2000/07/04 6.2.1 h- freq table output value (14 bits) h- freq( khz) 12mhz osc (hex / dec) 1 31.5 0fdeh / 4062 2 37.5 0d54h / 3412 3 43.3 0b8bh / 2955 4 46.9 0aa8h / 2728 5 53.7 094fh / 2383 6 60.0 0854h / 2132 7 68.7 0746h / 1862 8 75.0 06aah / 1706 9 80.0 063fh / 1599 10 85.9 05d1h / 1489 11 93.8 0554h / 1364 12 106.3 04b3h / 1203 6.2.2 v- freq table output value (12bits) v- freq(hz) 12mhz osc (hex / dec) 1 56 45ch / 1116 2 60 411h / 1041 3 70 37ch / 892 4 72 364h / 868 5 75 341h / 833 6 85 2dfh / 735 6.3 h/v present check the hpresent function checks the input hsync pulse, hpre flag is set when hsync is over 10khz or cleared when hsync is under 10hz. the vpresent function checks the input vsync pulse, the vpre flag is set when vsync is over 40hz or cleared when vsync is under 10hz. the hprchg interrupt is set when the hpre value changes. the vprchg interrupt is set when the vpre/ cvpre value change. however, the cvpre flag interrupt may be disabled when s/w disable the composite function. 6.4 h/v polarity detect the polarity functions detect the input hsync/vsync high and low pulse duty cycle. if the high pulse duration is longer than that of low pulse, the negative polarity is asserted; otherwise, positive polarity is asserted. the hplchg interrupt is set when the hpol value changes. the vplchg interrupt is set when the vpol value changes. 6.5 output hblank/vblank control and polarity adjust the hblank is the mux output of hsync, composite hpulse and self-test horizontal pattern. the vblank is the mux output of vsync, cvsync and self-test vertical pattern. the mux selection and output polarity are s/w controllable. the vblank output is cut off when vsync frequency is over 200hz. the hblank/vblank shares the output pin with p4.1/ p4.0. 6.6 self test pattern generator this generator can generate 4 display patterns for testing purpose, which are positive cross-hatch, negative cross-hatch, full white, and full black (showed as following figure). the hblank output frequency of the pattern can be chosen to 95.2khz, 63.5khz, 47.6khz and 31.75khz. the vblank output frequency of the pattern is 72hz or 60hz. it is originally designed to support monitor manufacturer to do burn-in test, or offer end-user a reference to check the monitor. the generator's output stout shares the output pin with p4.2.
myson technology MTV212A32 (rev. 1.2) revision 1.2 - 11 - 2000/07/04 display region positive cross-hatch negative cross-hatch full white full black
myson technology MTV212A32 (rev. 1.2) revision 1.2 - 12 - 2000/07/04 MTV212A32 self-test pattern timing 63.5khz, 60hz 47.6khz, 60hz 31.7khz, 60hz 95.2khz, 72hz time h dots time h dots time h dots time h dots hor. total time (a) 15.75us 1280 21.0us 1024 31.5us 640 10.5us 1600 hor. active time (d) 12.05us 979.3 16.07us 783.2 24.05us 488.6 8.03us 1224 hor. f. p. (e) 0.2us 16.25 0.28us 12 0.45us 9 0.14us 21 sync pulse width (b) 1.5us 122 2us 90 3us 61 1.0us 152 hor. b. p. (c) 2us 162.54 2.67us 110 4us 81.27 1.33us 203 time v lines time v lines time v lines time v lines vert. total time (o) 16.66ms 1024 16.66ms 768 16.66ms 480 13.89ms 1200 vert. active time (r) 15.65ms 962 15.65ms 721.5 15.65ms 451 13.03ms 1126 vert. f. p. (s) 0.063ms 3.87 0.063ms 2.9 0.063ms 1.82 0.052ms 4.5 sync pulse width (p) 0.063ms 3.87 0.063ms 2.9 0.063ms 1.82 0.052ms 4.5 vert. b. p. (q) 0.882ms 54.2 0.882ms 40.5 0.882ms 25.4 0.756ms 65 * 8 x 8 blocks of cross hatch pattern in display region. 6.7 hsync clamp pulse output the hclamp output is active by setting ? hclpe ? control bit. the hclamp ? s leading edge position, pulse width and polarity is s/w controllable. 6.8 vsync interrupt the MTV212A32 check the vsync input pulse and generate an interrupt at its leading edge. the vsync flag is set each time when MTV212A32 detects a vsync pulse. the flag is cleared by s/w writing a "0". 6.9 h/v sync processor register reg name addr bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 hvstus 40h (r) cvpre hpol vpol hpre vpre hoff voff hcnth 41h (r) hovf hf13 hf12 hf11 hf10 hf9 hf8 hcntl 42h (r) hf7 hf6 hf5 hf4 hf3 hf2 hf1 hf0 vcnth 43h (r) vovf vf11 vf10 vf9 vf8
myson technology MTV212A32 (rev. 1.2) revision 1.2 - 13 - 2000/07/04 vcntl 44h (r) vf7 vf6 vf5 vf4 vf3 vf2 vf1 vf0 hvctr0 40h (w) c1 c0 nohins hbpl vbpl hvctr2 42h (w) selft stf1 stf0 rt1 rt0 ste hvctr3 43h (w) clpeg clppo clpw2 clpw1 clpw0 intflg 48h (r/w) hprchg vprchg hplchg vplchg hfchg vfchg vsync inten 49h (w) ehpr evpr ehpl evpl ehf evf evsync hvstus (r ) : the status of polarity, present and static level for hsync and vsync. cvpre = 1 ? the extracted cvsync is present. = 0 ? the extracted cvsync is not present. h pol = 1 ? hsync input is positive polarity. = 0 ? hsync input is negative polarity. v pol = 1 ? vsync (cvsync) is positive polarity. = 0 ? vsync (cvsync) is negative polarity. h pre = 1 ? hsync input is present. = 0 ? hsync input is not present. v pre = 1 ? vsync input is present. = 0 ? vsync input is not present. h off* = 1 ? hsync input's off level is high. = 0 ? hsync input's off level is low. v off* = 1 ? vsync input's off level is high. = 0 ? vsync input's off level is low. *h off and v off are valid when h pre=0 or v pre=0. hcnth (r ) : h- freq counter's high bits. hovf = 1 ? h- freq counter is overflow, this bit is clear by h/w when condition removed. hf13 - hf8 : 6 high bits of h- freq counter. hcntl (r ) : h- freq counter's low byte. vcnth (r ) : v- freq counter's high bits. vovf = 1 ? v- freq counter is overflow, this bit is clear by h/w when condition removed. vf11 - 8 : 4 high bits of v- freq counter. vcntl (r ) : v- freq counter's low byte. hvctr0 (w ) : h/v sync processor control register 0. c1, c0 = 1, 1 ? select cvsync as the polarity, freq and vblank source. = 1,0 ? select vsync as the polarity, freq and vblank source. = 0,0 ? disable composite function. = 0,1 ? h/w auto switch to cvsync when cvpre=1 and vspre=0. nohins = 1 ? hblank has no insert pulse in composite mode. = 0 ? hblank has insert pulse in composite mode. hb pl = 1 ? negative polarity hblank output. = 0 ? positive polarity hblank output. vb pl = 1 ? negative polarity vblank output. = 0 ? positive polarity vblank output. hvctr2 (w ) : self-test pattern generator control. s elft = 1 ? enable generator. = 0 ? disable generator. stf1 ,stf0 = 1,1 ? 95.2khz(horizontal)/72hz(vertical) output selected.
myson technology MTV212A32 (rev. 1.2) revision 1.2 - 14 - 2000/07/04 = 1,0 ? 63.5khz(horizontal)/60hz(vertical) output selected. = 0 ,1 ? 47.6khz(horizontal) /60hz(vertical) output selected. = 0,0 ? 31.75khz(horizontal) /60hz(vertical) output selected. rt1, rt0= 0,0 ? positive cross-hatch pattern output. = 0,1 ? negative cross-hatch pattern output. = 1,0 ? full white pattern output. = 1,1 ? full black pattern output. ste = 1 ? enable stout output. = 0 ? disable stout output. hvctr3 (w ) : hsync clamp pulse control register. clpeg = 1 ? clamp pulse follows hsync leading edge. = 0 ? clamp pulse follows hsync trailing edge. clppo = 1 ? positive polarity clamp pulse output. = 0 ? negative polarity clamp pulse output. clpw2 : clpw0 : pulse width of clamp pulse is [(clpw2 :clpw0) + 1] x 0.167 m s for 12mhz x ? tal selection. intflg (w ) : interrupt flag. an interrupt event will set its individual flag, and, if the corresponding interrupt enable bit is set, the 8051 core's int1 source will be driven by a zero level. software must clear this register while serve the interrupt routine. hprchg= 1 ? no action. = 0 ? clear hsync presence change flag. vprchg= 1 ? no action. = 0 ? clear vsync presence change flag. hplchg = 1 ? no action. = 0 ? clear hsync polarity change flag. vplchg = 1 ? no action. = 0 ? clear vsync polarity change flag. hfchg = 1 ? no action. = 0 ? clear hsync frequency change flag. vfchg = 1 ? no action. = 0 ? clear vsync frequency change flag. vsync = 1 ? no action. = 0 ? clear vsync interrupt flag. intflg (r ) : interrupt flag. hprchg= 1 ? indicates a hsync presence change. vprchg= 1 ? indicates a vsync presence change. hplchg = 1 ? indicates a hsync polarity change. vplchg = 1 ? indicates a vsync polarity change. hfchg = 1 ? indicates a hsync frequency change or counter overflow. vfchg = 1 ? indicates a vsync frequency change or counter overflow. vsync = 1 ? indicates a vsync interrupt. inten (w ) : interrupt enable. ehpr = 1 ? enable hsync presence change interrupt. evpr = 1 ? enable vsync presence change interrupt. ehpl = 1 ? enable hsync polarity change interrupt. evpl = 1 ? enable vsync polarity change interrupt. ehf = 1 ? enable hsync frequency change / counter overflow interrupt. evf = 1 ? enable vsync frequency change / counter overflow interrupt. evsync = 1 ? enable vsync interrupt.
myson technology MTV212A32 (rev. 1.2) revision 1.2 - 15 - 2000/07/04 7. ddc & iic interface 7.1 ddc1 mode the MTV212A32 enters ddc1 mode after reset. in this mode, vsync is used as data clock. the hscl pin should remain at high. the data output to the hsda pin is taken from a shift register in MTV212A32. the shift register fetch data byte from the ddc1 data buffer (dbuf) then send it in 9 bits packet formats which includes a null bit (=1) as packet separator. the dbuf set the dbufi interrupt flag when the shift register read out the data byte from dbuf. software needs to write edid data to dbuf as soon as the dbufi is set. the dbufi interrupt is automatically cleared when software writes a new data byte to dbuf. the dbufi interrupt can be mask or enable by edbufi control bit. 7.2 ddc2b mode the MTV212A32 switches to ddc2b mode when it detects a high to low transition on the hscl pin. once MTV212A32 enters ddc2b mode, s/w can set iicpass control bit to allow host access eeprom directly. under such condition, the hsda and hscl are directly bypassed to isda and iscl pins. the other way to perform ddc2 function is to clear iicpass and config the slave a iic block to act as eeprom behavior. the slave a block's slave address can be chosen by s/w as 5-bits, 6-bits or 7-bits. for example, if s/w choose 5-bits slave address as 10100b, the slave iic block a will respond to slave address 10100xxb and save the 2 lsb " xx" in xfr. this feature enables MTV212A32 to meet pc99 requirement. the MTV212A32 will return to ddc1 mode if hscl is kept high for 128 vsync clock period. however, it will lock in ddc2b mode if a valid iic address (1010xxxb) has been detected on hscl/hsda bus. the ddc2 flag reflects the current ddc status, s/w may clear it by writing a "0" to it. 7.3 slave mode iic function block the slave mode iic block is connected to hsda and hscl pins. this block can receive/transmit data using iic protocol. there are 2 slave addresses MTV212A32 can respond to. s/w may write the slvaadr/slvbadr register to determine the slave addresses. the slavea address can be configured to 5-bits, 6-bits or 7-bits by s/w setting the slvabs1 and slvabs0 control bits. in receive mode, the block first detects iic slave address match condition then issues a slvami/ slvbmi interrupt. if the matched address is slave a, MTV212A32 will save the matched address's 2 lsb bits to slvalsb1 and slvalsb0 register. the data from hsda is shifted into shift register then written to rcabuf/rcbbuf register when a data byte is received. the first byte loaded is word address (slave address is dropped). this block also generates a rcai/rcbi (receive buffer full interrupt) every time when the rcabuf/rcbbuf is loaded. if s/w can't read out the rcabuf/rcbbuf in time, the next byte in shift register will not be written to rcabuf/rcbbuf and the slave block return nack to the master. this feature guarantees the data integrity of communication. the wadra/ wadrb flag can tell s/w that if the data in rcabuf/rcbbuf is a word address. in transmit mode, the block first detects iic slave address match condition then issues a slvami/ slvbmi interrupt. in the mean time, the slvalsb1/slvalsb0 is also updated if the matched address is slave a, and the data pre-stored in the txabuf/txbbuf is loaded into shift register, result in txabuf/txbbuf empty and generates a txai/txbi (transmit buffer empty interrupt). s/w should write the txabuf/txbbuf a new byte for next transfer before shift register empty. fail to do this will cause data corrupt. the txai/txbi occurs every time when shift register reads out the data from txabuf/txbbuf. the slvami/ slvbmi is cleared by writing "0" to corresponding bit in intflg register. the rcai/rcbi is cleared by reading rcabuf/rcbbuf. the txai/txbi is cleared by writing txabuf/txbbuf. if the control bit enscl is set, the block will hold hscl low until the rcai/rcbi/txai/txbi is cleared. *please see the attachments about "slave iic block timing". 7.4 master mode iic function block the master mode iic block can be connected to the isda /iscl pins or the hsda/hscl pins, select by msel control bit. its speed can be selected to 50khz-400khz by s/w setting the miicf1/miicf0 control bit. the software program can access the external iic device through this interface. since the edid/vdif data and the display information share the common eeprom, precaution must be taken to avoid bus conflicting while msel=0. in ddc1 mode or iicpass=0, the iscl/isda is controlled by MTV212A32 only. in ddc2 mode
myson technology MTV212A32 (rev. 1.2) revision 1.2 - 16 - 2000/07/04 and iicpass flag is set, the host may access the eeprom directly. software can test the hscl condition by reading the hbusy flag, which is set in case of hscl=0, and keeps high for 100us after the hscl's rising edge. s/w can launch the master iic transmit/receive by clearing the p bit. once p=0, MTV212A32 will hold hscl low to isolate the host's access to eeprom. a summary of master iic access is illustrated as follows. 7.4.1. to write iic device 1. write mbuf the slave address. 2. set s bit to start. 3. after the MTV212A32 transmit this byte, a mbufi interrupt will be triggered. 4. program can write mbuf to transfer next byte or set p bit to stop. * please see the attachments about "master iic transmit timing". 7.4.2. to read iic device 1. write mbuf the slave address. 2. set s bit to start. 3. after the MTV212A32 transmit this byte, a mbufi interrupt will be triggered. 4. set or reset the macko flag according to the iic protocol. 5. read out mbuf the useless byte to continue the data transfer. 6. after the MTV212A32 receives a new byte, the mbufi interrupt is triggered again. 7. read mbuf also trigger the next receive operation, but set p bit before read can terminate the operation. * please see the attachments about "master iic receive timing". reg name addr bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 iicctr 00h (r/w) ddc2 macko p s iicstus 01h (r) wadrb wadra slvrwb sackin slvs slvalsb1 slvalsb0 iicstus 02h (r) mackin hifreq hbusy intflg 03h (r) txbi rcbi slvbmi txai rcai slvami dbufi mbufi intflg 03h (w) slvbmi slvami mbufi inten 04h (w) etxbi ercbi eslvbmi etxai ercai eslvami edbufi embufi mbuf 05h (r/w) master iic receive/transmit data buffer rcabuf 06h (r) slave a iic receive buffer txabuf 06h (w) slave a iic transmit buffer slvaadr 07h (w) enslva slave a iic address rcbbuf 08h (r) slave b iic receive buffer txbbuf 08h (w) slave b iic transmit buffer slvbadr 09h (w) enslvb slave b iic address dbuf 0ah (w) ddc1 transmit data buffer iicctr (r/w ) : iic interface control register. ddc2 = 1 ? MTV212A32 is in ddc2 mode, write "0" can clear it. = 0 ? MTV212A32 is in ddc1 mode. macko = 1 ? in master receive mode, nack is returned by MTV212A32. = 0 ? in master receive mode, ack is returned by MTV212A32. s, p = - , 0 ? start condition when master iic is not during transfer. = x, - ? stop condition when master iic is not during transfer. = 1, x ? will resume transfer after a read/write mbuf operation. = x, 0 ? force hscl low and occupy the master iic bus. * a write/read mbuf operation can be recognized only after 10us of the mbufi flag's rising edge. iicstus (r ) : iic interface status register. wadrb = 1 ? the data in rcbbuf is word address. wadra = 1 ? the data in rcabuf is word address. slv rwb = 1 ? current transfer is slave transmit
myson technology MTV212A32 (rev. 1.2) revision 1.2 - 17 - 2000/07/04 = 0 ? current transfer is slave receive sackin = 1 ? the external iic host respond nack. slvs = 1 ? the slave block has detected a start, cleared when stop detected. slvalsb1 ,slvalsb0 : the 2 lsb which host send to slave a block. mackin = 1 ? master iic bus error, no ack received from the slave iic device. = 0 ? ack received from the slave iic device. hifreq = 1 ? MTV212A32 has detected a higher than 200hz clock on the vsync pin. hbusy = 1 ? host drives the hscl pin to low. intflg (w ) : interrupt flag. a interrupt event will set its individual flag, and, if the corresponding interrupt enable bit is set, the 8051 int1 source will be driven by a zero level. software must clear this register while serve the interrupt routine. slvbmi = 1 ? no action. = 0 ? clear slvbmi flag. slvami = 1 ? no action. = 0 ? clear slvami flag. mbufi = 1 ? no action. = 0 ? clear master iic bus interrupt flag ( mbufi). intflg (r ) : interrupt flag. txbi = 1 ? indicates the txbbuf need a new data byte, clear by writing txbbuf. rcbi = 1 ? indicates the rcbbuf has received a new data byte, clear by reading rcbbuf. slvbmi = 1 ? indicates the slave iic address b match condition. txai = 1 ? indicates the txabuf need a new data byte, clear by writing txabuf. rcai = 1 ? indicates the rcabuf has received a new data byte, clear by reading rcabuf. slvami = 1 ? indicates the slave iic address a match condition. dbufi = 1 ? indicates the ddc1 data buffer need a new data byte, clear by writing dbuf. mbufi = 1 ? indicates a byte is sent/received to/from the master iic bus. inten (w ) : in terrupt enable. etxbi = 1 ? enable txbbuf interrupt. ercbi = 1 ? enable rcbbuf interrupt. eslvbmi = 1 ? enable slave address b match interrupt. etxai = 1 ? enable txabuf interrupt. ercai = 1 ? enable rcabuf interrupt. eslvami = 1 ? enable slave address a match interrupt. edbufi = 1 ? enable ddc1 data buffer interrupt. embufi = 1 ? enable master iic bus interrupt. mbuf (w ) : master iic data shift register, after start and before stop condition, write this register will resume MTV212A32's transmission to the iic bus. mbuf (r ) : master iic data shift register, after start and before stop condition, read this register will resume MTV212A32's receiving from the iic bus. rcabuf (r ) : slave iic block a receive data buffer. txabuf (w ) : slave iic block a transmit data buffer. slvaadr (w ) : slave iic block a's enable and address. enslva = 1 ? enable slave iic block a. = 0 ? disable slave iic block a. bit6-0 : slave iic address a to which the slave block should respond.
myson technology MTV212A32 (rev. 1.2) revision 1.2 - 18 - 2000/07/04 rcbbuf (r ) : slave iic bloc k b receive data buffer. txbbuf (w ) : slave iic block b transmit data buffer. slvbadr (w ) : slave iic block b's enable and address. enslvb = 1 ? enable slave iic block b. = 0 ? disable slave iic block b. bit6-0 : slave iic address b to which the sl ave block should respond. 8. low power reset (lvr) & watchdog timer when the voltage level of power supply is below 4.0v for a specific time, the lvr will generate a chip reset signal. after the power supply is above 4.0v, lvr maintain in reset state for 144 xtal cycle to guarantee the chip exit reset condition with a stable x'tal oscillation. the watchdog timer automatically generates a device reset when it is overflow. the interval of overflow is 0.25 sec x n, where n is a number from 1 to 8, and can be programmed via register wdt(2:0). the timer function is disabled after power on reset, user can activate this function by setting wen, and clear the timer by set wclr. 9. a/d converter the MTV212A32 is equipped with three 6-bit a/d converters, s/w can select the current convert channel by setting the sadc1/sadc0 bit. the refresh rate for the adc is osc freq./12288. the adc compare the input pin voltage with internal vdd*n/64 voltage (where n = 0 - 63). the adc output value is n when pin voltage is greater than vdd*n/64 and smaller than vdd*(n+1)/64. reg name addr bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 adc 10h (w) enadc sadc3 sadc2 sadc1 sadc0 adc 10h (r) adc convert result wdt 18h (w) wen wclr wdt2 wdt1 wdt0 wdt (w ) : watchdog timer c ontrol register. wen = 1 ? enable watchdog timer. wclr = 1 ? clear watchdog timer. wdt2: wdt0 = 0 ? overflow interval = 8 x 0.25 sec. = 1 ? overflow interval = 1 x 0.25 sec. = 2 ? overflow interval = 2 x 0.25 sec. = 3 ? overflow interval = 3 x 0.25 sec. = 4 ? overflow interval = 4 x 0.25 sec. = 5 ? overflow interval = 5 x 0.25 sec. = 6 ? overflow interval = 6 x 0.25 sec. = 7 ? overflow interval = 7 x 0.25 sec. adc (w ) : adc control. enadc = 1 ? enable adc. sadc0 = 1 ? select adc0 pin input. sadc1 = 1 ? select adc1 pin input. sadc2 = 1 ? select adc2 pin input. sadc3 = 1 ? no action. adc (r ) : adc convert result.
myson technology MTV212A32 (rev. 1.2) revision 1.2 - 19 - 2000/07/04 memory map of xfr reg name addr bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 iicctr 00h (r/w) ddc2 macko p s iicstus 01h (r) wadrb wadra slvrwb sackin slvs slvalsb1 slvalsb0 iicstus 02h (r) mackin hifreq hbusy intflg 03h (r) txbi rcbi slvbmi txai rcai slvami dbufi mbufi intflg 03h (w) slvbmi slvami mbufi inten 04h (w) etxbi ercbi eslvbmi etxai ercai eslvami edbufi embufi mbuf 05h (r/w) master iic receive/transmit data buffer rcabuf 06h (r) slave a iic receive buffer txabuf 06h (w) slave a iic transmit buffer slvaadr 07h (w) enslva slave a iic address rcbbuf 08h (r) slave b iic receive buffer txbbuf 08h (w) slave b iic transmit buffer slvbadr 09h (w) enslvb slave b iic address dbuf 0ah (w) ddc1 transmit data buffer adc 10h (w) enadc sadc3 sadc2 sadc1 sadc0 adc 10h (r) adc convert result wdt 18h (w) wen wclr wdt2 wdt1 wdt0 da0 20h (r/w) pulse width of pwm dac 0 da1 21h (r/w) pulse width of pwm dac 1 da2 22h (r/w) pulse width of pwm dac 2 da3 23h (r/w) pulse width of pwm dac 3 da4 24h (r/w) pulse width of pwm dac 4 da5 25h (r/w) pulse width of pwm dac 5 da6 26h (r/w) pulse width of pwm dac 6 da7 27h (r/w) pulse width of pwm dac 7 da8 28h (r/w) pulse width of pwm dac 8 da9 29h (r/w) pulse width of pwm dac 9 da10 2ah (r/w) pulse width of pwm dac 10 da11 2bh (r/w) pulse width of pwm dac 11 da12 2ch (r/w) pulse width of pwm dac 12 da13 2dh (r/w) pulse width of pwm dac 13 padmod 30h (w) da13e da12e da11e da10e ad3e ad2e ad1e ad0e padmod 31h (w) p56e p55e p54e p53e p52e p51e p50e padmod 32h (w) hiice iiice hlfve hlfhe hclpe p42e p41e p40e option 33h (w) pwmf div253 fclke iicpass enscl msel miicf1 miicf0 option 34h (w) slvabs1 slvabs0 xbank 35h (r/w) xbnk2 xbnk1 xbnk0 port4 38h (w) p42 p41 p40 port5 39h (r/w) p56 p55 p54 p53 p52 p51 p50 hvstus 40h (r) cvpre hpol vpol hpre vpre hoff voff hcnth 41h (r) hovf hf13 hf12 hf11 hf10 hf9 hf8 hcntl 42h (r) hf7 hf6 hf5 hf4 hf3 hf2 hf1 hf0 vcnth 43h (r) vovf vf11 vf10 vf9 vf8 vcntl 44h (r) vf7 vf6 vf5 vf4 vf3 vf2 vf1 vf0 hvctr0 40h (w) c1 c0 nohins hbpl vbpl hvctr2 42h (w) selft stf1 stf0 rt1 rt0 ste hvctr3 43h (w) clpeg clppo clpw2 clpw1 clpw0 intflg 48h (r/w) hprchg vprchg hplchg vplchg hfchg vfchg vsync inten 49h (w) ehpr evpr ehpl evpl ehf evf evsync
myson technology MTV212A32 (rev. 1.2) revision 1.2 - 20 - 2000/07/04 electrical parameters 1. absolute maximum ratings at: ta= 0 to 70 o c, vss=0v name symbol range unit maximum supply voltage vdd -0.3 to +6.0 v maximum input voltage vin -0.3 to vdd+0.3 v maximum output voltage vout -0.3 to vdd+0.3 v maximum operating temperature topg 0 to +70 o c maximum storage temperature tstg -25 to +125 o c 2. allowable operating conditions at: ta= 0 to 70 o c, vss=0v name symbol min. max. unit supply voltage vdd 4.5 5.5 v input "h" voltage vih1 0.4 x vdd vdd +0.3 v input "l" voltage vil1 -0.3 0.2 x vdd v operating freq. fopg - 15 mhz 3. dc characteristics at: ta=0 to 70 o c, vdd=5.0v, vss=0v name symbol condition min. typ. max. unit output "h" voltage, open drain pin voh1 ioh=0ua 4 v output "h" voltage, 8051 i/o port pin voh2 ioh=-50ua 4 v output "h" voltage, cmos output voh3 ioh=-4ma 4 v output "l" voltage vol iol=5ma 0.45 v active 18 24 ma idle 1.3 4.0 ma power supply current idd power-down 50 80 ua rst pull-down resistor rrst vdd=5v 150 250 kohm pin capacitance cio 15 pf 4. ac characteristics at: ta=0 to 70 o c, vdd=5.0v, vss=0v name symbol condition min. typ. max. unit crystal frequency fxtal 12 mhz pwm dac frequency fda fxtal=12mhz 46.875 94.86 khz hs input pulse width thipw fxtal=12mhz 0.3 8 us vs input pulse width tvipw fxtal=12mhz 3 us hsync to hblank output jitter thhbj 5 ns h+v to vblank output delay tvvbd fxtal=12mhz 8 us vs pulse width in h+v signal tvcpw fxtal=12mhz 20 us sda to scl set up time tdcsu 200 - - ns sad to scl hold time tdch 100 - - ns
myson technology MTV212A32 (rev. 1.2) revision 1.2 - 21 - 2000/07/04 scl high time tsclh 500 - - ns scl low time tscll 500 - - ns start condition setup time tsu:sta 500 - - ns start condition hold time thd:sta 500 - - ns stop condition setup time tsu:sto 500 - - ns stop condition hold time thd:sto 500 - - ns test mode condition in normal application, users should avoid the MTV212A32 entering its test mode, outlined as follow: test mode a: reset=1 & da9=1 & da8=0 & sto=0 test mode b: reset's falling edge & da9=1 & da8=0 & sto=1 package dimension 1. 40-pin pdip 600 mil 52.197mm +/-0.127 15.494mm +/-0.254 2.540mm 0.457mm +/-0.127 1.270mm +/-0.254 1.981mm +/-0.254 3.81mm +/-0.127 1.778mm +/-0.127 0.254mm (min.) 3.302mm +/-0.254 13.868mm +/-0.102 16.256mm +/-0.508 0.254mm +/-0.102 5 o ~7 0 6 o +/-3 o t dch t dcsu t t t t t t su :sta hd :sta hd :sto su :sto sckl sckh data interface timing (i 2 c)
myson technology MTV212A32 (rev. 1.2) revision 1.2 - 22 - 2000/07/04 2. 42 pin sdip unit: mm 3. 44 pin plcc unit: pin #1 hole 0.653 +/-0.003 0.690 +/-0.005 0.690 +/-0.005 0.653 +/-0.003 0.045*45 0 0.180 max. 0.020 min. 0.610 +/-0.02 0.500 0.070 0.070 7 0 typ. 0.010 0.050 typ. 0.013~0.021 typ. 0.026~0.032 typ. dimension in mm symbol min nom max a 3.937 4.064 4.2 a1 1.78 1.842 1.88 b1 0.914 1.270 1.118 d 36.78 36.83 36.88 e1 13.945 13.970 13.995 f 15.19 15.240 15.29 eb 15.24 16.510 17.78 0 7.5 15 15.494mm +/-0.254 13.868mm +/-0.102 16.256mm +/-0.508 0.254mm +/-0.102 5 o ~7 0 6 o +/-3 o
myson technology MTV212A32 (rev. 1.2) revision 1.2 - 23 - 2000/07/04 ordering information standard configurations: prefix part type package type rom size (k) mtv 212a n: pdip s: sdip v: plcc 32 part numbers: prefix part type package type rom size (k) mtv 212a n 32 mtv 212a s 32 mtv 212a v 32

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